1. Field of the Invention
The invention relates to a method and apparatus for digital-to-analog signal conversion, more particularly to a digital-to-analog signal conversion method and apparatus suitable for high-order low-pass filtering.
2. Description of the Related Art
Referring to FIG. 1, a conventional digital-to-analog converter 1 is shown to include an operational amplifier 11, a plurality of capacitors (C1, C2, . . . , Cn), a plurality of first switches (S10), a plurality of second switches (S11), a plurality of third switches (S12), and a fourth switch (S13). The operational amplifier 11 has a grounded non-inverting input 111, an inverting input 112, an output 113, and a feedback capacitor (CFB) connected between the inverting input 112 and the output 113. Each of the capacitors (C1, C2, . . . , Cn) has a first capacitor terminal connected to one of the first switches (S10) and one of the second switches (S11), and a second capacitor terminal connected to one of the third switches (S12) and to the fourth switch (S13). Each of the first switches (S11) connects the first capacitor terminal of a respective one of the capacitors (C1, C2, . . . , Cn) to a positive or negative reference voltage (Vr+ or Vrxe2x88x92). Each of the second switches (S11) connects the first capacitor terminal of a respective one of the capacitors (C1, C2, . . . , Cn) to the output 113 of the operational amplifier 11. Each of the third switches (S12) connects the second capacitor terminal of a respective one of the capacitors (C1, C2, . . . , Cn) to a ground terminal. The fourth switch (S13) connects the second capacitor terminals of the capacitors (C1, C2, . . . , Cn) to the inverting input 112 of the operational amplifier 11.
In the converter 1, digital-to-analog conversion is performed in two time periods. During the first time period, the first and third switches (S10, S12) are closed, whereas the second and fourth switches (S11, S13) are opened, thereby charging the capacitors (C1, C2, . . . , Cn) using either the positive or negative reference voltage (Vr+ or Vrxe2x88x92). Particularly, if an associated data bit of an input data byte is at a high logic level (i.e., 1), the first switch (S10) connects the respective capacitor (C1, C2, . . . , Cn) to the positive reference voltage (Vr+), and if the associated data bit of the input data byte is at a low logic level (i.e., 0), the first switch (S10) connects the respective capacitor (C1, C2, . . . , Cn) to the negative reference voltage (Vrxe2x88x92). Subsequently, during the second time period, the first and third switches (S10, S12) are opened, whereas the second and fourth switches (S11, S13) are closed. At this time, the capacitors (C1, C2, . . . , Cn) and the feedback capacitor (CFB) are connected in parallel between the inverting input 112 and the output 113 of the operational amplifier 11, thereby redistributing charges among the capacitors (C1, C2, . . . , Cn) and the feedback capacitor (CFB) for conducting n-to-1 digital-to-analog signal conversion.
However, if the above-described conventional converter 1 is expanded to achieve a high-order low-pass filtering effect, i.e., xe2x88x923 DB low frequency cutoff frequency setting, the required capacitance value of the feedback capacitor (CFB) will accordingly increase, thereby resulting in a larger layout area requirement.
FIG. 2 shows another conventional digital-to-analog converter 2. In the converter 2, each of an inverting input 211 and a non-inverting input 212 of an operational amplifier 21 is connected to two switch-capacitor arrays 22, such as that shown in FIG. 2A. The conversion function thereof is:       1    ⁢          /        ⁢    2    ⁢          (              1        +                  Z                      -            1                              )            1    +                  C        FB                    C        DAC              -                  (                              C            FB                                C            DAC                          )            ⁢              Z                  -          1                    
where CDAC=2 (C1+C1+ . . . +C31). It is evident that the capacitance value of the feedback capacitors (CFB) increase with that of CDAC. Since CDAC is the total capacitance of C1, C2, . . . , C31, a very large CFB value will result, which leads to increased volume. In addition, too many capacitors are required, which is not economical.
Therefore, the main object of the invention is to provide a digital-to-analog signal conversion method and apparatus suitable for high-order low-pass filtering and capable of overcoming the aforesaid drawbacks of the prior art.
According to one aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
a plurality of first capacitors;
a charging unit connected to the first capacitors during a first time period for charging each of the first capacitors in accordance with an associated data bit of an input data byte;
a second capacitor;
a switch set for connecting the first capacitors to the second capacitor during a second time period that follows the first time period; and
a switch unit for connecting the second capacitor to the operational amplifier during a third time period that follows the second time period.
According to another aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
a plurality of first capacitors;
a charging unit connected to the first capacitors during a first time period for charging each of the first capacitors in accordance with an associated data bit of an input data byte;
a plurality of second capacitors;
a switch set for connecting the first capacitors to the second capacitors during a second time period, wherein clock pulses of the second time period follow clock pulses of the first time period, and wherein the switch set connects the first capacitors to each of the second capacitors in sequence under the control of the clock pulses of the second time period; and
a switch unit for connecting the second capacitors simultaneously to the operational amplifier during a third time period that follows the second time period.
According to another aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
two first capacitor sets, each including a plurality of first capacitors;
two charging units connected respectively to the first capacitor sets during a first time period for charging each of the first capacitors of the respective one of the first capacitor sets in accordance with an associated data bit of an input data byte;
two second capacitors;
a switch set for connecting each of the first capacitor sets to a respective one of the second capacitors during a second time period that follows the first time period; and
a switch unit for connecting the second capacitors simultaneously to the operational amplifier during a third time period that follows the second time period;
the operational amplifier having two inputs and two outputs, the switch unit connecting each of the second capacitors between a respective one of the inputs and a respective one of the outputs of the operational amplifier during the third time period.
According to another aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
a plurality of first capacitors;
first and second charging units connected to the first capacitors during a first time period, wherein each of the first capacitors is charged by the first charging unit in accordance with an associated data bit of an input data byte during a first clock pulse of the first time period, and is charged by the second charging unit in accordance with the associated data bit of the input data byte during a second clock pulse of the first time period;
two second capacitors;
a switch set for connecting the first capacitors to the second capacitors during a second time period, wherein the switch set connects the first capacitors to one of the second capacitors after the first clock pulse of the first time period and to the other of the second capacitors after the second clock pulse of the first time period; and
a switch unit for connecting the second capacitors simultaneously to the operational amplifier during a third time period that follows the second time period.
According to another aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
two first capacitor sets, each including a plurality of first capacitors;
two charging units connected respectively to the first capacitor sets during a first time period for charging each of the first capacitors of the respective one of the first capacitor sets in accordance with an associated data bit of an input data byte;
two second capacitor sets, each including a plurality second capacitors;
a switch set for connecting the first capacitor sets to the second capacitor sets respectively during a second time period, wherein clock pulses of the second time period follow clock pulses of the first time period, and wherein the switch set connects the first capacitors of each of the first capacitor sets to each of the second capacitors of the respective one of the second capacitor sets in sequence under the control of the clock pulses of the second time period; and
a switch unit for connecting the second capacitor sets simultaneously to the operational amplifier during a third time period that follows the second time period.
According to another aspect of the invention, a digital-to-analog converter comprises:
an operational amplifier;
a first capacitor set including a plurality of first capacitors;
first and second charging units connected to the first capacitor set during a first time period, wherein each of the first capacitors is charged by the first charging unit in accordance with an associated data bit of an input data byte during a first clock pulse of the first time period, and is charged by the second charging unit in accordance with the associated data bit of the input data byte during a second clock pulse of the first time period;
two second capacitors sets each including a plurality of second capacitors;
a switch set for connecting the first capacitor set alternately to the second capacitor sets during a second time period, wherein clock pulses of the second time period follow clock pulses of the first time period, and wherein the switch set connects the first capacitor set to each of the second capacitors of the second capacitor sets in sequence under the control of the clock pulses of the second time period; and
a switch unit for connecting the second capacitor sets simultaneously to the operational amplifier during a third time period that follows the second time period.
According to another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first time period, charging each of a plurality of first capacitors in accordance with an associated data bit of an input data byte;
during a second time period that follows the first time period, connecting the first capacitors to a second capacitor; and
during a third time period that follows the second time period, connecting the second capacitor to an operational amplifier.
According to another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first time period, charging each of a plurality of first capacitors in accordance with an associated data bit of an input data byte;
during a second time period having clock pulses that follow clock pulses of the first time period, connecting the first capacitors to each of a plurality of second capacitors in sequence under the control of the clock pulses of the second time period; and
during a third time period that follows the second time period, connecting the second capacitors simultaneously to an operational amplifier.
According to another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first time period, charging each of a plurality of first capacitors of two first capacitor sets in accordance with an associated data bit of an input data byte;
during a second time period that follows the first time period, connecting each of the first capacitor sets to a respective one of two second capacitors; and
during a third time period that follows the second time period, connecting the second capacitors simultaneously to an operational amplifier such that each of the second capacitors is connected between a respective one of two inputs and a respective one of two outputs of the operational amplifier.
According to another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first clock pulse of a first time period, charging each of a plurality of first capacitors using a first charging unit in accordance with an associated data bit of an input data byte;
during a second clock pulse of the first time period, charging each of the first capacitors using a second charging unit in accordance with the associated data bit of the input data byte;
during a second time period, connecting the first capacitors to one of two second capacitors after the first clock pulse of the first time period and to the other of the second capacitors after the second clock pulse of the second time period; and
during a third time period that follows the second time period, connecting the second capacitors simultaneously to an operational amplifier.
According to another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first time period, charging each of two first capacitor sets in accordance with an input data byte;
during a second time period having clock pulses that follow clock pulses of the first time period, connecting each of the first capacitor sets to each second capacitor of a respective second capacitor set in sequence under the control of the clock pulses of the second time period; and
during a third time period that follows the second time period, connecting the second capacitor sets simultaneously to an operational amplifier.
According to yet another aspect of the invention, a digital-to-analog signal conversion method comprises:
during a first clock pulse of a first time period, charging each of a plurality of first capacitors of a first capacitor set using a first charging unit in accordance with an associated data bit of an input data byte;
during a second clock pulse of the first time period, charging each of the first capacitors using a second charging unit in accordance with the associated data bit of the input data byte;
during a second time period having clock pulses that follow the clock pulses of the first time period, connecting the first capacitor set alternately to two second capacitor sets such that the first capacitor set is connected to each of a plurality of second capacitors of the second capacitor sets in sequence under the control of the clock pulses of the second time period; and
during a third time period that follows the second time period, connecting the second capacitor sets simultaneously to an operational amplifier.